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Phd Thesis, on, low Power Vlsi design : Power, of Critical
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power dissipation is achieved with low overhead in computational time. Pdf nicola00.pdf - other, download (3MB). Archive (ZIP) nicola00.zip - other, download (719kb more information. Published date: October 2000, organisations: University of southampton, Electronics computer Science. Identifiers, local EPrints ID: 254107, uri: /id/eprint/254107, pure uuid: catalogue record, date deposited:, last modified: 09:54. Export record, ascii citationAtomBibtexdata cite xmldublin CoreDublin CoreEP3 xmlendNotehtml citationhtml citationhtml listjsonmetsmodsmpeg-21 didlopenurl contextObjectOpenurl contextObject in xmlreferReference managerSimple metadata. Nicolici, university divisions, download statistics. Downloads from ePrints over the past year. Other digital versions may also be available to download.
Since the proposed test application strategy depends only on controlling primary input change time, power is minimised with no empire penalty in test area, performance, test efficiency, test application time or volume of test data. Furthermore, it is shown that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. To achieve power savings in large scan sequential circuits a new test set independent multiple scan chain-based technique which employs a new design for test (DFT) architecture and a novel test application strategy, is presented. The technique has been validated using benchmark examples, and it has been shown that power is minimised with low computational time, low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power minimisation techniques for testing low power vlsi circuits using built-in self-test (bist) at rtl. First, it is important to overcome the shortcomings associated with traditional bist methodologies. It is shown how a new bist methodology for rtl data paths using a novel concept called test compatibility classes (TCC) overcomes high test application time, bist area overhead, performance degradation, volume of test data, fault-escape probability, and complexity of the testable design space exploration. Second, power minimisation in bist rtl data paths is achieved by analysing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms.
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(2000) Power Minimisation Techniques for Testing Low Power vlsi circuits (Phd dissertation). University of southampton, : University of southampton, doctoral Thesis. Record type: Thesis (Doctoral abstract, testing low power very large business scale integrated (vlsi) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the vlsi design flow. The first part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change (bpic) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits.